The Million Dollar 3D Question

Originally posted on 3D InCites, by Francoise von Trapp

With all the latest hubbub about FinFets (or as Intel calls them, TriGate transistors) , there seems to be some confusion in terminology, leading to confusion in who’s doing what first. First and foremost, the technology Intel claims to have pioneered is 3D transistors, also known generically as FinFets. TSMC has also announced that they will move forward with FinFets. What people need to understand here, is while TriGate or FinFets ultimately do create three dimensional structures on a chip, the term “3D Chips” refers to stacked die interconnected using through silicon via (TSV) technology. It’s important to understand the difference, because from production processes, design, and market adoption perspectives, these are two completely different animals.

This was explained further to me by Jean-Marc Chery, CTO, ST Microelectronics, who addressed the attendees at the 2011 Leti Annual Review in Grenoble on June 26. Chery was clarifying St Microelectronics’ position on semiconductor technology developments based on different technology nodes. STM has been working side-by-side with Leti to develop Ultra-thin Body and Box on fully depleted silicon-on-insulator substrate(UTBB/FDSOI), a technology enabling a 2 D planar transistor on fully depleted SOI substrate. At 20nm, Intel and TSMC have announced they will manufacture FinFet transisitors (TriGate). However, ST Micro believes that 2D planar transistor solutions can be pursued. First a standard 20nm LP (2D Planar transistor on bulk CMOS) process will offer a mainstream solution addressing density, performance at nominal operating voltage and low power. Moreover, a boosted 20nm technology can be derived from the 20nm bulk CMOS technology by taking advantage of the UTBB/FDSOI** electrostatic properties.

“We believe that a 20nm UTBB/FDSOI will offer the appropriate boost solution for wireless SOCs needs evolutions, thanks to the performance that is equivalent to 22nm TriGate from Intel , but at a much lower cost in terms of process development and manufacturing, and providing simpler design porting from former platform on bulk to FDSOI.” explained Chery. “Consequently, this will allow us to provide a performing 20nm UTBB/FDSOI offer aligned with the market timing and needs. At 28nm ST Micro could anticipate this offer to customers as a differentiator from other companies with its 2D planar SOI technology.”

At 14nm, however, Chery says something must be done to change the transistor structure because “transistor source/drain junction depth cannot scale down beyond 20nm as far as gate length and gate dielectric thickness because electrostatic behavior of transistor is no longer controlled, and the transistor On/Off transition is poorly controlled by the gate switch when applying polarization on the drain. He says the choice is either to remain with 2D planar design but absolutely with UTBB/FDSOI, or go to 3D FinFet design. Intel and TSMC will go to FinFet because they’ve already started down that road.

ST Micro is part of the International Semiconductor Alliance, which also includes IBM, Global Foundries, Samsung and Toshiba. The alliance has not yet announced their technology choice, but ST Micro will support whatever the alliance decides and will play key role, explains Chery.

Part of the confusion between 3D transistors and 3D integration technologies has come about because 3D integration has also been touted as a way to scale further. However, while we were on the topic of St. Micro’s technology positions, (and since 3D InCites has always been focused on 3D integration and packaging) I felt compelled to get Chery’s take on St. Micro’s position regarding 2.5D and 3D IC. He said that at 20nm, they see 3D more or less ramping up – and certainly ramping at 14nm for interconnect and packaging. “It’s going to be a matter of cost-of-ownership of the various solutions,” he said. “Separating digital and anolog functions and stacking using copper pillars and/or silicon interposers e is a lower cost option than full SOC. Interposer technology is the first step towards full 3D integration.”

There is, however, a performance link between 3D transistors and 3D TSVs. During his presentation at D43D, Georg Kimmich, STE, talked about the performance needs of tablets and smartphones. By 2013, he says graphics performance of high-end smartphones and tablet devices will be limited by memory bandwidth. He says display resolution will quadruple for tablet devices and use significantly more bandwidth. This will drive the need for wide I/O DRAM on logic, which is expected be adopted in the 2014-2015 timeframe.

The proverbial “memory wall” has been an issue for quite some time, and increased performance of microprocessors is just increasing the need for faster, shorter, more powerful interconnects, ie: TSVs. Putting all this together in my head, I was compelled to ask Kimmich the million dollar question: Will the improved performance resulting from FInFets (TriGate) 3D transistors increase this memory wall issue, thereby also increasing the need for 3D TSVs? The answer: Yes, absolutely. So there’s the connection between 3D transistors and 3D Integration technologies. And all this could lead to 3D TSVs in wide I/O DRAM on Logic sooner than we think. – F.v.T.

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