The evolutionary path of MEMS manufacturing guides Okmetic’s R&D activities

Due to the versatility of MEMS technologies the industry still lacks a comprehensive roadmap


Contributed by Markku Tilli, Okmetic

The MEMS technology has evolved a lot during the past few decades. However, it still lacks the same kind of exhaustive roadmap that the semiconductor technology has had already since the 1990’s. The International Technology Roadmap for Semiconductors, ITRS, has expanded over the years, and it covers nearly 20 chapters and well over thousand pages now. It includes forecasts on all aspects from materials to packaging and from design to environmental issues. SEMI has also organized sessions on standardization for some years now and the industry has established some globally accepted technical standards.

The MEMS industry still has a long road to travel to get to the same position where the semiconductor industry is at the moment. The need for a MEMS roadmap was only recognized in the MEMS Industry Group’s Metric workshop in March 2010. Since then the MEMS Industry Group has been working to develop a roadmap, and they have started the massive project with the standardization of testing methods. In the future, these testing standards and test method specifications could act as the nuclei of an International Technology Roadmap for MEMS, ITRM, which could mimic the structure of the semiconductor roadmap, ITRS.

One does not need to look into a crystal ball to predict, that it will still take years to develop a comprehensive roadmap, as it took with the semiconductors. What makes the task challenging is the versatility of different MEMS platforms and technologies.

Another approach is the starting material

However, there are other ways to approach the roadmap matter. Maybe it would be easier to start by investigating elements of the MEMS technology. Starting material could be this kind of area.

At first sight microfluidics, optical, and inertial devices have many differences. But the common nominator is the starting material, silicon wafers. Similar silicon wafers are used in different kinds of technologies. Over the years the silicon wafers have developed along with the technologies, and they still continue to do so.

The early technology platforms used bare silicon wafers, single side polished for surface MEMS and double side polished for bulk MEMS.  In recent years, more and more wafers of the SOI-family have taken share in the market. First there were SOI wafers, then SOI wafers with buried cavities (C-SOI) and the following step is to incorporate TSV´s, through silicon vias, in the wafer structure. Yole Développement has stated that there is no roadmap in MEMS manufacturing, but it follows an evolutionary path. In the light of MEMS and silicon wafer history this conclusion seems logical.

Okmetic’s SOI wafers are the result of its long-term R&D activities


Okmetic has always had a strong focus on the future and a clear vision of the evolutionary development path of silicon wafers. The company’s R&D work is guided by a thorough understanding of customer needs and material solutions. Okmetic also participates in national and international research projects which help the company recognize the early trends in the field and to schedule and direct its product development in the right way. For example, Okmetic’s SOI wafers are the result of a well-directed and scheduled long-term R&D work.

SOI wafers have many advantages

Okmetic started developing its SOI wafers already in the 1990´s. By the end of the decade, the SOI technology platform was considered attractive especially for the inertial devices. Nowadays SOI has become a popular technology platform also among many other devices for several reasons. The SOI wafer process that bonds two silicon wafers together and then thins the device layer sets very few limitations for wafer resistivity, device layer and substrate wafer orientation, oxide thickness, and device layer thickness.

It is possible to use very high resistivity wafers that have low RF-losses and high IR-transmittance or very low resistivity wafers that have high conductivity, EMC shielding, and less charging effects etc. These things can also be combined so that the substrate has low resistivity and device layer high resistivity. In addition, the anisotropic properties of silicon can be utilized in a similar way to combine different wafer orientations including surface misorientation.

Also, it should be noted that SOI wafer is already a partial package. The device is shielded from the substrate side, and the only thing that has to be added is a cap wafer with or without TSV´s depending on the design. Many designs have the problem of being susceptible to device bending over specified temperature range. However, this temperature dependent bending can be minimized by designing a symmetrical structure. The thinning of the device can be made symmetrically, too. Both substrate and cap wafer can be thinned with the established technologies used in silicon wafer processing.

It is also possible to use new processing technologies in creating SOI structures. ALD, atomic layer deposition, is a good example of attractive new technologies. ALD produces very uniform layers even on “hidden” surfaces, like cavities through holes or trenches. There are established processes for instance for aluminum oxide which is very effective etch stop for DRIE or for titanium nitride that is conductive. Some metals, for example ruthenium, can be deposited as well. The Finnish ALD research cluster has also some other new ALD processes under development.

Okmetic’s R&D benefits all product areas

Okmetic is allocating most of its R&D resources to MEMS related work. However, this does not mean that other application areas do not get attention. The results that we have got, for instance, in very heavily doped or almost intrinsic material can also be directly applied in the semiconductor area. The very heavily phosphorus doped, 1 mOhm-cm range ingots typically used in MEMS products are increasingly being used in advanced power semiconductors as well. And, the same thing applies for heavy boron or arsenic doping. The only difference is that the wafers targeted at power semiconductors are usually single side polished instead of double side polished or SOI wafers that are used in MEMS products.

Consequently, Okmetic’s R&D work benefits all product areas because as formerly mentioned many of the results gained in the MEMS area can be applied directly or implicitly in the semiconductor area as well.


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